1. Field of the Invention
The present invention relates to semiconductor memory devices.
2. Description of Related Art
Today, nonvolatile memories are widely used in system-on-chip (SoC) devices incorporated in a variety of applications. In particular, in applications with low active factors (such as in sensor networks and in living body monitoring), tight restrictions are imposed on electric power consumption during a standby period with a view to reducing battery capacity and system module size.
If, for the sake of discussion, a volatile memory (e.g., SRAM (static random-access memory)) is used as a data buffer in an application as mentioned above, the leak current through it may greatly affect the total electric power consumption of the system. On the other hand, when a nonvolatile memory is used as a data buffer, data can be held on a nonvolatile basis without supply of electric power, and this greatly contributes to power saving during a standby period. Thus, it can be said that a nonvolatile memory is very suitable as a data buffer in an application with a low active factor.
As a nonvolatile memory, FeRAM (ferroelectric random-access memory) is in practical use (e.g., in non-contact IC cards), which employs ferroelectric capacitors. FeRAM, however, is not quite satisfactory in driving speed and electric power consumption during an active period, and in durability.
To overcome the shortcomings of FeRAM, there has been proposed shadow memory having a 6T-4C structure (or a 6T-2C structure) which is a combination of SRAM having a 6T structure with a ferroelectric capacitor (hereinafter referred to as ferroelectric shadow memory).
A ferroelectric shadow memory operates as an SRAM having a 6T structure during an active period (during a data read/write operation), but stores data in a ferroelectric capacitor and becomes nonvolatile during a standby period. Thus, with a ferroelectric shadow memory, it is possible to achieve both high-speed operation during an active period and power saving (leak current reduction) during a standby period.
Examples of conventional technology related to the foregoing are seen in Non-Patent Documents 1 and 2 identified below.    Non-Patent Document 1: S. Masui, W. Yokozeki, et al., “Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall”, In Proc. of IEEE CICC, pp. 403-406, 2003.    Non-Patent Document 2: T. Miwa, J. Yamada, et al., “NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors”, IEEE JSSC, vol. 36, no. 3, pp. 522-527, 2001.
Inconveniently, however, compared with SRAM having a 6T structure, ferroelectric shadow memory has the following shortcomings: (1) high electric power consumption during an active period; (2) slow operation speed during an active period; and (3) difficulty detecting defects in ferroelectric capacitors due to production variations.